This invention relates to calibrating an output signal level of a target integrated circuit, and more particularly, to a calibration scheme applied to a data processing apparatus (e.g., an MPEG chip) for determining a target firmware trim value set to the data processing apparatus.
The process of fabricating integrated circuits (ICs) on a semiconductor substrate, such as a silicon wafer, is highly complex and consists of a large number of steps. Each step involves many process parameters that must be tightly controlled in order to obtain consistent and accurate results. There are, however, physical factors that may cause unintentional deviations in the process at any step.
The deviations in the process may be a function of time that is between successive wafers, or between various parts of any wafer, or both. When any of these process deviations becomes excessive, singly or in combination, the actual characteristics of the fabricated ICs are deviated from the ideal characteristics. For example, an MPEG chip implemented in multimedia playback apparatuses is typically formed of integrated semiconductor components. However, as known to those skilled in this art, because process characteristics are very difficult to control and keep stable, so that even within a single process, components fabricated within the same process will exhibit different electrical characteristics, causing characteristics of the components to vary greatly from original design requirements. Suppose that the MPEG chip is designed for outputting a TV-compliant signal, such as a composite video signal (or referred to as a CVBS signal), to drive a TV set to display the desired images thereon. Therefore, a video digital-to-analog converter (DAC) is implemented within the MPEG chip to convert decoded/processed digital video data into the composite video signal. Additionally, an external video buffer, equipped with a predetermined driving strength, is coupled to the MPEG chip for buffering the composite video signal outputted from the video DAC to the destination TV set. However, due to the process variation, circuit component accuracy, and manufacture deviation, the video output level deviation occurs. Taking the well-known NTSC composite video signal for example, a white level is defined to be equal to 100 IRE (e.g., 1V), and the sync tip level is defined to be −40 IRE (e.g., 0V). The unit of measurement for the amplitude is in terms of an IRE unit, where 140 IRE is representative of a peak-to-peak voltage of 1V. If the output signal amplitude is deviated from the desired level, the display quality of images shown on the TV set might be degraded greatly. As a result, there is a need for a calibration scheme that would compensate the MPEG chip, especially the video DAC implemented therein, for the undesired output signal amplitude deviation.